1. Field of the Invention
The present invention relates to an encoding and/or decoding circuit for run-length-limited coding
The run-length-limited coding is used, for example, for writing data at a high density on a rotating disc memory medium such as a magnetic disc medium. In the encoding operation for the run-length-limited coding, each bit sequence having a predetermined length in an original data is encoded to a code having another predetermined length before the data is written in a magnetic memory medium. One of the run-length-limited coding systems which is most frequently used in recent rotating disc devices, is called one-by-seven (1,7) coding. Various types of the (1,7) coding systems are explained in the U.S. Pat. No. 4,488,142 to P. A. Franaszek, and the U.S. Pat. No. 4,413,251 to R. L. Adler et al.
In encoding circuits for the run-length-limited coding, the above bit sequence having a predetermined length in an original data is supplied, synchronized with a clock, as an input to an encoder which converts the input to the above code having another predetermined length, and the output of the encoder is transferred, for example, to a data writing portion in a magnetic disc device, synchronized with another clock. Both the above operations for supplying of the input bit sequence and the transferring of the output, must be carried out within one cycle of the encoding operation. Since the number of the bits in the above input and output of the encoder are different, two clock signals having different frequencies must be provided for the above operations for supplying the input bit sequence and transferring the output of the encoder.
Similarly, in decoding circuits for the run-length-limited coding, bit sequence of coded data having the above other predetermined length, which is read from a data read portion in the rotating disc device, is supplied as an input to a decoder which converts the input to a bit sequence having the above predetermined length in the original data, synchronized with a clock, and the output of the decoder is transferred, for example, to a read data output portion of the rotating disc device, synchronized with another clock. Both the above operations for supplying of the input bit sequence and the transferring of the output, must be carried out within one cycle of the encoding operation. Since the number of the bits in the above input and output of the decoder are different, two clock signals having different frequencies must be provided for the above operations for supplying the input bit sequence and transferring the output of the decoder.
Further, since both the clock signals must synchronize with the above cycle of the encoding operation, both the above clock signals used for supplying the input bit sequence to the encoder or decoder and transferring the output of the encoder or decoder, are usually generated from a common clock. Conventionally, the above two clock signals are generated from a clock which is generated by a variable frequency oscillator (VFO), and therefore, the frequency of the clock is at least equal to the least common multiple of the frequencies of the two clock signals.
However, recently, high speed data transfer is required in rotating disc devices as well as other data storage devices. To realize the high speed data transfer, the frequencies of the above-mentioned two clock signals used for supplying the input bit sequence and transferring the output of the encoder or decoder, must be increased.
However, generally, the oscillation in the variable frequency oscillator is liable to become unstable when the frequency is high, and therefore, precise circuit elements must be used for constructing the variable frequency oscillator for high frequency, and additional complex circuitry is required to be provided for making the operation of the variable frequency oscillator stable, and these are factors which increase cost and power consumption. Further, when the frequency of the system clock is high, the circuitry around the variable frequency oscillator must be constructed of high speed circuit elements, which also increases cost and power consumption.
Therefore, to realize the above high-speed operation in supplying the input bit sequence to the encoder or decoder and transferring the output of the encoder or decoder, using a clock having not so high a frequency is required.
2. Description of the Related Art
FIG. 1 shows the relationships between the above-mentioned bit sequence in the original data and the corresponding coded data in the one-by-seven coding in the encoding operation, which is disclosed in the U.S. Pat. No. 4,488,142 to P. A. Franaszek and U.S. Pat. No. 4,866,544 to S. Hashimoto. As shown in FIG. 1, in the one-by-seven coding, a pair of two successive bits are converted into a code data comprised of three bits, and in the coding operation of each pair of the original data, a bit preceding the pair and a next one or two bits following the pair are used for the coding. In FIG. 1, b0 and b1 denote a pair of bits in the original data which is under the coding operation, b2 and b3 denote a next pair of bits in the original data following the bit b1, s0, s1, and s2 denote coded data corresponding to the pair of bits b0 and b1, x denotes a don't care bit (i.e., the bit is not used for the coding) 00 denotes any pair of bits except 00, and 01 denotes any pair of bits except 01.
In the prior art, a construction as shown in FIG. 2 is used for carrying out the above encoding. FIG. 2, reference numeral 1 denotes a variable frequency oscillator, 2 denotes a 1/3 frequency divider, 3 denotes a 1/2 frequency divider, 4, 6 and 8 each denote a shift register, 5 denotes an AND gate, and 7 denotes a coder.
In the construction of FIG. 2, the variable frequency oscillator 1 generates a system clock of 108 MHz frequency, where a servo clock or READ DATA signal is used as a reference clock. The system clock of 108 MHz is supplied to the 1/3 frequency divider 2 and the 1/2 frequency divider 3, and a clock of 36 MHz and another clock of 54 MHz are from the 1/3 frequency divider 2 and the 1/2 frequency divider 3, respectively. In addition, the clocks of 36 MHz and 54 MHz are applied to input terminals of the AND gate 5 to generate a parallel load control signal having a frequency of 18 MHz.
First, a set of the original data which is to be written in the rotating disc medium (which is denoted by WRITE DATA in FIG. 2), for example, one byte of data, is set in parallel in the shift register 4. Then, each bit of the shift register 4 is serially output from the shift register 4 to enter the shift register 6 synchronized with the above clock of 36 MHz. When a pair of bits is written in the shift register 6, the pair of bits is loaded in the coder 7 at the timing of the parallel load control signal. Corresponding to the input, the coder 7 outputs coded data comprised of three bit in accordance with the relationships shown in FIG. 1. Then, the output of the coder 7 is loaded in parallel in the shift register 8. Finally, each bit of the data loaded in the shift register 8 is serially output therefrom to be supplied to a data writing portion (not shown) in the rotating disc device synchronized with the above clock of 54 MHz.
As explained before, in the construction of FIG. 2, the system clock of 108 MHz is needed to be generated by the variable frequency oscillator 1 to generate the clocks of 36 MHz and 54 MHz for supplying the input bit sequence to the encoder 7 and transferring the output of the encoder 7. The timing of the above three clocks of 108 MHz, 54 MHz, and 36 MHz are shown in FIG. 3.
Similarly, in decoding circuits for the run-length-limited coding, a bit sequence of coded data having the above another predetermined length, which is read from a data read portion in the rotating disc device, is supplied as an input to a decoder which converts the input to a bit sequence having the above predetermined length in the original data, synchronized with a clock, and the output of the decoder is transferred to a read data output portion of the rotating disc device, synchronized with another clock. Both the above operations for supplying of the input bit sequence and the transferring of the output, must be carried out within one cycle of the encoding operation. Since the number of the bits in the above input and output of the decoder are different, two clock signals having different frequencies must be provided for the above operations for supplying the input bit sequence and transferring the output of the decoder.
FIG. 4 shows the relationships between the bit sequence of coded data comprised of three bits, which is read from a data read portion in the rotating disc device, and the corresponding bit sequence of a pair of bits in the decoded data, in the decoding operation in the one-by-seven coding, which is disclosed in the U.S. Pat. No. 4,488,142 to P. A. Franaszek. As shown in FIG. 4, in the one-by-seven coding, code data comprised of three bits are decoded into a pair of two successive bits, and in the decoding operation of each pair of the original data, a bit preceding the pair and a next one or two bits following the pair are used for the coding. In FIG. 4, s0, s1, and s2 denote coded data which is under the decoding operation, s3, s4, and s5 denote coded data which follows the three bits s0, s1, and s2, s-1, s-2, and s-3 which precedes the three bits s0, s1, and s2, b0 and b1 denote a pair of bits in the decoded data corresponding to the three bits s0, s1 and s2, x denotes a don't care bit, and 00 denotes any pair of bits except 00.
In the prior art, a construction as shown in FIG. 5 is used for carrying out the above decoding. In FIG. 5, reference numeral 11 denotes a variable frequency oscillator, 12 denotes a 1/3 frequency divider, 13 denotes a 1/2 frequency divider, 14 denotes an AND gate, 15 and 17 each denote a shift register, and 16 denotes a decoder.
In the construction of FIG. 5, the construction for generating clocks comprised of the variable frequency oscillator 11 for generating a system clock of 108 MHz frequency, the 1/3 frequency divider 2 for generating a clock of 36 MHz, the 1/2 frequency divider 3 for generating a clock of 54 MHz, and the AND gate 14, are the same as the corresponding construction in FIG. 2.
In the construction of FIG. 5, first, a set of the coded data which has been read from a rotating disc medium in the rotating disc device (which is denoted by READ DATA in FIG. 5), comprised of three bits, is serially entered in the shift register 17 synchronized with the clock of 54 MHz. When each bit sequence comprised of three bits is set in the shift register 17, the content of the shift register 17 is loaded in parallel in the decoder 16 at the timing of the parallel load control signal of 18 MHz. Corresponding to the input, the decoder 16 outputs decoded data comprised of a pair of bits in accordance with the relationships shown in FIG. 4. Then, the output of the decoder 16 is loaded in parallel in the shift register 15. Finally, each bit of the data loaded in the shift register 15 is serially output therefrom to be supplied to a data reading portion (not shown) in the rotating disc device synchronized with the above clock of 36 MHz.
As explained before, in the construction of FIG. 5, the system clock of 108 MHz is needed to be generated in the variable frequency oscillator 1 to generate the clocks of 36 MHz and 54 MHz for supplying the input bit sequence to the decoder 16 and transferring the output of the decoder 16.
Further, FIG. 6 shows the construction of an encoder/decoder which operates as an encoder when writing data in the rotating disc medium, and operates as a decoder when reading data from the rotating disc medium. As readily understood from the construction of FIG. 6, the construction of FIG. 6 includes both the constructions of FIGS. 2 and 5, and the constructions included in FIG. 6 respectively operate in the same manner as the constructions of FIGS. 2 and 5.
To solve the above-mentioned problem, some attempts have been made as follows.
The Japanese Unexamined Patent Publication No. 63-144464 discloses a technique wherein first and second variable frequency oscillators, a 1/3 frequency divider, and a 1/2 frequency divider are provided. The first variable frequency oscillator generates a clock having a frequency of 54 MHz using the servo clock or the read data signal as a reference clock, and the clock is frequency-divided in the 1/3 frequency divider to obtain a clock having a frequency of 18 MHz. The second frequency divider generates another clock having a frequency of 36 MHz. The frequency of the output clock of the second frequency divider is divided by the 1/2 frequency divider to obtain a clock having a frequency of 18 MHz, and the second frequency divider maintains the frequency of 36 MHz by comparing the output clock of the 1/2 frequency divider with the output clock of 1/3 frequency divider as a reference clock.
However, in the above technique, two variable frequency oscillators are necessary, and the cost is increased.
The Japanese Unexamined Patent Publication No. 61-250875 discloses a technique wherein a 2/3 frequency divider is constructed as an analog circuit, and the 2/3 frequency divider generates a clock having a frequency of 36 MHz from a clock having a frequency of 54 MHz which is generated by a variable frequency oscillator using the servo clock or the read data signal as a reference clock.
However, in the above technique, an analog circuit must be used for constructing the 2/3 frequency divider, and therefore, a troublesome adjustment is required for the analog circuit, the construction as an LSI is difficult, and the cost for constructing the circuit is increased.
The Japanese Unexamined Patent Publication No. 63-144465 discloses a technique wherein a clock "substantially" having a frequency of 36 MHz is generated by removing one pulse in every successive three pulses in a clock having a frequency of 54 MHz.
However, in the above technique, the intervals of successive two pulses in the clock "substantially" having a frequency of 36 MHz are the same as the intervals of corresponding two pulses in the clock having a frequency of 54 MHz. That is, microscopically, the actual maximum frequency in which the successive pulses in the above clock "substantially" having a frequency of 36 MHz appear, is equal to 54 MHz. Therefore, the construction of a portion of the circuitry which operates synchronized with the above clock "substantially" having a frequency of 36 MHz, must be designed so that the portion can operate synchronized with the above successive pulses appearing at 54 MHz in the clock "substantially" having a frequency of 36 MHz. That is, the portion of the circuitry must be constructed by circuit elements designed for operating in a relatively higher speed, and this increases power consumption in that portion and the cost for constructing that portion.